1. Field of the Invention
The present invention relates to an integrated converter for use as an integrated analog-to-digital converter or an integrated digital-to-analog converter.
2. Description of the Prior Art
Analog-to-digital (A/D) converters include an integrated A/D converter, a successive approximation A/D converter, and a parallel approximation A/D converter among others. The integrated A/D converter (see Japanese Laid-Open Patent Publication No. 60-79811, for example) is capable of converting signals with high accuracy, as with the integrated digital-to-analog (D/A) converter.
FIGS. 1A and 1B of the accompanying drawings show a conventional three-stage cascade integrated A/D converter for converting audio input signals in a frequency range of about 20 kHz. The integrated A/D converter shown in FIGS. 1A and 1B has an A/D converter unit 1 constructed as an integrated circuit (IC). An analog input signal VI supplied through a input terminal 2 to the A/D converter unit 1 is converted into a serial digital signal DS which is outputted from an output terminal 3. The A/D converter unit 1 is supplied with an integrating clock signal MCK, an output clock signal BCK, and an integration start signal WCK through respective terminals 4, 5, 6.
A system clock signal SCK having a frequency of 12 MHz (more accurately, 12.288 MHz) is supplied to an input terminal 7. The frequency of the system clock signal SCK is divided by a frequency divider 8 into a 1/6 frequency, which is then divided by a frequency divider 9 into a 1/32 frequency. The system clock signal SCK is transmitted through a buffer 10A as the integrating clock signal MCK (see FIG. 2A). The output signal from the frequency divider 8 is transmitted through a buffer 10B as the output clock signal BCK (see FIGS. 2B and 2C) which has a frequency of about 2 MHz. The output signal from the frequency divider 9 is transmitted through a buffer 10C as the integration start signal WCK (see FIG. 4D) which has a frequency of 64 kHz.
In the A/D converter unit 1, the input signal VI is supplied to an inverting input terminal of a differential amplifier 14 through a resistor 11 and a first input terminal and an output terminal of a switch circuit 13. The first input terminal of the switch circuit 13 is connected to the output terminal of the differential amplifier 14 through a resistor 12 which has the same resistance as that of the resistor 11. The inverting input terminal of the differential amplifier 14 is connected to the output terminal thereof through an integrating capacitor 15. The differential amplifier 14 has a noninverting input terminal connected to ground. The switch circuit 13 also has second, third, and fourth input terminals supplied with respective reference signals VR1, VR2, VR3 through respective resistors 16, 17, 18. If the input signal VI is of a positive voltage, then the reference signals VR1, VR2, VR3 are of negative voltages. With the resistors 16, 17, 18 being of equal resistances, since 2.sup.5 =32, the following equations are satisfied: EQU VR1=32.times.VR2, VR2=32 VR3.
A converted output signal VC produced from the differential amplifier 14 is supplied to inverting input terminals of comparators 19, 20, 21 whose noninverting input terminals are supplied with reference signals having a voltage level El, a voltage level E2, and a ground level, respectively. Output signals from the respective comparators 19, 20, 21 and the integrating clock signal MCK are supplied to a clock signal selector 22. The voltage levels El, E2 are of negative voltages, respectively. If the level difference between an input voltage and a 1-bit output voltage is expressed as .DELTA.E, then the following equations are satisfied: EQU E1=32.times.E2, E2=32.times..DELTA.E.
The clock signal selector 22 supplies the integrating clock signal MCK to a high-order counter 23 when the output signals from the comparators 19, 20, 21 are of a high level of "1", to an intermediate-order counter 24 when only the output signals from the comparators 20, 21 are of a high level of "1", and to a low-order counter 25 when only the output signal from the comparator 21 is of a high level of "1". Each of the counters 23, 24, 25 comprises a 5-bit binary counter. Output count signals from the counters 23, 24, 25 correspond respectively to high-order five bits, intermediate-order five bits, and low-order five bits, of a converted 15-bit output signal. These parallel output count signals from the counters 23, 24, 25 and the output clock signal BCK are supplied to a shift register 26. The shift register 26 supplies its output signal as the serial digital signal DS to the output terminal 3 in synchronism with the output clock signal BCK.
The A/D converter unit 1 also includes a control circuit 27 which is supplied with the integrating clock signal MCK and the integration start signal WCK. The control circuit 27 is also supplied with a signal indicative of the address of the counter 23, 24, or 25 which is being supplied with the integrating clock signal MCK, from the clock signal selector 22. When the integration start signal WCK is of a low level of "0", the control circuit 27 controls the switch circuit 13 to select the first input terminal to integrate the input signal VI. When the integration start signal WCK is of a high level of "1", the control circuit 27 controls the switch circuit 13 to select one of the reference signals VR1, VR2, VR3 depending on the selection by the clock signal selector 22 of the counter 23, 24, or 25. Immediately after the integration start signal WCK goes high, the control circuit 27 clears the counts of the counters 23, 24, 25 through a line (not shown). Immediately after the integration start signal WCK goes low, the control circuit 27 loads the parallel data into the shift register 26.
Operation of the conventional integrated A/D converter shown in FIGS. 1A and 1B will be described below with reference to FIGS. 2A through 2E. FIGS. 2C through 2E show signal waveforms in a period T5 (FIG. 2A) corresponding to 96.times.2 pulses of the integrating clock signal MCK. The integration start signal WCK is obtained by dividing the frequency of the integrating clock signal MCK by 6.times.32, and the period T5 of the integrating clock signal MCK is equivalent to the period of the integration start signal WCK.
During an interval in which the signal WCK is of a level of "0" in the period T5, the switch circuit 13 selects the input signal VI. Since the capacitor 15 is quickly charged with a current of the signal VI, the converted output signal VC from the differential amplifier 14 becomes a signal which is opposite in polarity and equal in magnitude to the signal VI, as indicated by the solid-line curve 28 in FIG. 2E. Therefore, the input signal VI is sampled during this interval. When the signal WCK thereafter goes high, the control circuit 27 clears the counts of the counters 23, 24, 25, and then causes the switch circuit 13 to select any one of the reference signals VR1, VR2, VR3 depending on the address information from the clock signal selector 22.
More specifically, as shown in FIG. 2E, during an interval T1 in which the converted output signal VC is lower than the level E1, the switch circuit 13 selects the reference signal VR1, and the high-order counter 23 is supplied with the integrating clock signal MCK. While the reference signal VR1 is being integrated by the capacitor 15 (i.e., discharged thereby in the illustrated arrangement), pulses of the clock signal MCK are counted by the high-order counter 23. During an interval T2 in which the converted output signal VC is of a level between the levels El, E2, the reference signal VR2 and the intermediate-order counter 24 are selected. During an interval T3 in which the converted output signal VC is of a level between the level E2 and the ground level 0, the reference signal VR3 and the low-order counter 25 are selected. The integrated value produced by the capacitor 15 as the converted output signal VC becomes zero, the low-order counter 25 stops counting the pulses. Therefore, a binary code composed of a serial combination of the 5-bit output signals from the counters 23, 24, 25 serves as the digitally converted data of the input signal VI. Stated otherwise, according to the three-stage integrating arrangement shown in FIG. 1, since 2.sup.5 =32 and 3 .times.32=96 for 15-bit digital conversion, only 96 pulses are required to be used as the integrating clock signal MCK. If 15-bit digital conversion were to be effected by one-stage integration, however, since 2.sup.1 5 =32768, 32678 pulses are required for use as the integrating clock signal MCK.
When the integration start signal WCK becomes "0", the control circuit 27 loads the 15-bit data into the shift register 26, and enables the switch circuit 13 to select the input signal VI again. The shift register 26 supplies the 15-bit data serially to the output terminal 3 in synchronism with the output clock signal BCK, and at the same time the input signal VI starts being sampled.
If the A/D converter is used to convert an ordinary audio signal, then another integrator comprising a differential amplifier 14 is connected parallel to the existing differential amplifier 14, for integrating a right channel input signal, the existing differential amplifier 14 integrating a left channel input signal, which may be the input signal VI. While the integration start signal WCK is being of a level of "1", the right channel input signal is sampled, and while the integration start signal WCK is being of a level of "0", the right channel input signal is converted into a digital signal. The shift register 26 alternately supplies the left channel 15-bit data and the right channel 15-bit data to the output terminal 3. In this manner, two-channel input signals are successively converted into digital signals at 64 kHz.
When the input signal VI is reduced in amplitude, the sampled converted output signal VC is of a waveform as indicated by the broken-line curve 29 in FIG. 2E, and the integrated voltage gradients during analog-to-digital conversion are the same as those when the input signal VI is higher in amplitude.
Recently, research has been carried out to incorporate in portable battery-operated electrocardiographs A/D converters for converting analog bioelectric signals, such as electrocardiographic signals, into digital signals for digital signal processing. The A/D converters for such medical applications are supplied with input signals whose frequencies range from 0 to 100 Hz, and are required to have a minimum electric power requirement. If A/D converters for audio signal processing use can be used as A/D converters for medical use, then it will be possible to lower the cost of developing and manufacturing electrocardiographs.
ICs of the CMOS configuration consume electric energy at positive- or negative-going edges of pulses, and hence their electric energy consumption generally increases in proportion to the frequencies of various clock signals used in the ICs. Therefore, inasmuch as the frequencies of input signals such as bioelectric signals are about 1/100 of audio frequencies, when the frequencies of the integrating clock signal MCK, the output clock signal BCK, and the integration start signal WCK in the A/D converter shown in FIGS. 1A and 1B are reduced to 1/100, the electric power consumption by the A/D converter unit 1 as it is used in medical applications may be reduced to 1/100 of the electric power consumption for audio signal processing applications.
When the frequency of the integrating clock signal MCK in FIGS. 1A and 1B is to be reduced to 1/100, it is necessary to reduce the integrated voltage gradients to 1/100 (the time constant is increased 100 times) in the periods T1 through T3 shown in FIG. 2E. However, if the time constant is increased 100 times, the capacitance of the integrating capacitor 15 is too large or the integrating current is too small, resulting in unstable operation. Conversely, if the integrated voltage gradients were too small, then it would be difficult to determine the end of an integration process through zero-crossing detection of the converted output voltage VC, with the results that a conversion error would be increased and the tendency to induce noise would also be increased.
In order to set a sampling frequency for the input signal VI in the A/D converter shown in FIGS. 1A and 1B to 640 Hz, for example, for bioelectric signals, it may be desirable to sample and convert the input signal VI once during the period T5 (1/T5=64 kHz) as is the case with the conventional arrangement, and to introduce the finally produced 15-bit digital signal in a period T4 (T4=100 T5). However, though the sampling frequency for the input signal is reduced to 1/100, the electric power consumption cannot be reduced since it remains the same as that of the conventional A/D converter.